Need uniform ED coat in CED process in the recess areas

Hello sirs I humbly feel that it's really a great time to interact with you wizards. in our CED ⇦ huh? process, we are encountering a major paint problem poor E'coat deposition (dipping process) defect in the sill outer panel of the car body because of "rust" in the non-coverage area of coating. this is not occurring in the sill outer panels we use which are provided with wax holes.

I'm really baffled whether the problem is with the process parameter settings or the mechanical alignment or settings .

the process parameters settings we use in our CED process are :

%NVM = 18.7
pH = 5.94
CONDUCTIVITY = 1827 uS
P/B RATIO = 0.16-0.25
BATH TEMPERATURE = 30.7
APPLIED VOLTAGE = INLET POINT = 0 V
OUTLET VOLTAGE = 100 V
MAIN BUS = 235 V
CURRENT = INLET = 0/350 amps
MAIN = 950 amps

when we change the inlet voltage, paint defect "hash marks" start appearing in the car bodies . we are planning to increase the %NVM or the inlet voltage , WILL IT SOLVE THE PROBLEM !
generously give me your valuable suggestions .

ACRONYMS:

ED = electrodeposition ["e-coating", "electropainting"]

CED = cathodic electrodeposition

NVM = non-volatile material

P/B ratio = binder-pigment ratio